As the functionality requirements of today's electronic products increase, the IC designs associated with these products also become increasingly more complicated. Examples of such IC designs include very large-scale integration (VLSI) circuits such as microprocessor chips (including those provided by Sun Microsystems, Inc., of Palo Alto, Calif.). As these designs become more compact, in part, to incorporate additional functionality in the same floor space, voltage variations at the transistor level quickly become a significant problem for designers. More specifically, a challenging issue facing today's IC designers is reducing direct current (DC) and alternating current (AC) voltage variations at the transistors of IC chips.
In AC voltage variations, the voltage variation is directly proportional to inductance and rate of current variation. Thus, as the current swings increase, so do the voltage variations. Large current swings may result, for example, from clock-gating (i.e., turning off/on) various blocks in a chip, high switching instruction and data patterns, and wide instruction and data buses. In DC voltage variations, the voltage variation is generally directly proportional to the resistance of a given path. Thus, as the resistance in a path increases, so does the voltage drop in that path.
Accordingly, problems associated with the prior art include increased power consumption and decreased performance due in part to unstable and/or unpredictable voltage levels at transistors of a chip. Also, having an unstable and/or unpredictable voltage at the transistor level may decrease the reliability of a chip.
Another issue facing today's IC designers is that the current bump placement techniques may require that bumps be located over alpha sensitive circuitry because nearly all bumps contain lead, which omits alpha particles. This is highly undesirable because alpha particles can interfere with the operation of an IC.
FIG. 1 illustrates an exemplarily cross-sectional view of a power grid 100 in accordance with the prior art. A first power bus 102 has bumps 104a, 104b, and 104c thereon. A ground bus 106 has bumps 108a, 108b, and 108c thereon. A second power bus 110 includes bumps 112a, 112b, and 112c. As illustrated in FIG. 1, the ground bus 106 may be located between the first power bus 102 and the second power bus 110. Alternatively, a power bus may be located between two ground buses (not shown). As illustrated in FIG. 1, bumps from different buses are substantially aligned. For example, the bump 104a is aligned with bumps 108a and 112a. 